個人資訊 | 建國科大 ee-class 數位學習系統

建國科大 ee-class 數位學習系統

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建國科大 ee-class 數位學習系統

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相關辦法
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個人資訊

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基本資訊

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個人基本資訊

編輯

基本資訊

基本資訊

姓名

許重傑

個人網站

http://lms.ctu.edu.tw/s0302

自我介紹

出生於鹿港小鎮靠海邊的小地方(黑橋、兔仔寮)，不折不扣的鄉下人!

學校經歷

國立臺灣科技大學 / 電子工程系 (博士)

工作經歷

1. 東華影像股份有限公司 / 品質保證處處長 (2003-07 ~ 2005-01)
2. 南開技術學院電子工程系 / 助理教授 (2000-08 ~ 2003-07)
3. 國立台灣科技大學電子工程系 / 普物實習助教 (1996-09 ~ 1999-06, 兼職)
4. 矽品精密股份有限公司開發處開發課 / 高級工程師 (1996-03 ~ 1996-09)
5. 華邦電子股份有限公司品保處可靠工程部 / 副工程師 (1995-06 ~ 1996-02)

個人著作：

期刊論文

1.	許重傑, "Synopsys Sentaurus TCAD模擬軟體之安裝與其透過遠端連線執行方式之研究," 建國科大學報, Jan, 2018.
2.	許重傑, "超大型積體電路技術實習課程學習成效評估之研究," 科技與工程教育學刊, ISSN: 10257578, Mar, 2015.
3.	Chorng-Jye Sheu, "New Compact and Time-Efficient Reliability Physics Model for p-Type Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, Nov, 2010.
4.	Chorng-Jye Sheu, "Electron Substrate and Gate Current Modeling for Single-Drain Buried-Channel p-Type Metal-Oxide-Semiconductor-Field-Effect-Transistors Including Tunneling Mechanisms," Japanese Journal of Applied Physics, Nov, 2008.
5.	Chorng-Jye Sheu, "Compact Hot-Electron Induced Oxide Trapping Charge and Post-Stress Drain Current Modeling for Buried-Channel pMOSFETs," Japanese Journal of Applied Physics, Aug, 2008.
6.	Chorng-Jye Sheu, "Study of the Characteristics of Contrast Ratio and Response time for Small Size a-Si TFT LCDs," Journal of Chienkuo Technology University, Oct, 2007.
7.	Chorng-Jye Sheu, Sheng-Lyang Jang, "Modeling of electron gate current and post-stress drain current of p-type silicon-on-insulator MOSFETs," Solid-State Electronics*, Apr, 2003.
8.	Chorng-Jye Sheu, Sheng-Lyang Jang , "A MOSFET gate current model with the direct tunneling mechanism," Solid-State Electronics*, Oct, 2000.
9.	Chorng-Jye Sheu, Sheng-Lyang Jang , "A physics-based electron gate current model for fully depleted SOI MOSFETs," Solid-State Electronics*, Oct, 2000.
10.	Sheng-Lyang Jang , Chorng-Jye Sheu, Chorng-Bin Twu, "A compact drain-current model for stacked-gate flash memory cells," Solid-State Electronics*, Aug, 2000.
11.	Sheng-Lyang Jang , Chorng-Jye Sheu, "A non-local gate current and oxide trapping charge generation model for lightly doped drain and single-drain nMOSFETs," Solid-State Electronics*, Jul, 2000.
12.	Chwan-Gwo Chyau, Sheng-Lyang Jang, Chorng-Jye Sheu, "A physics-based short-channel SOI MOSFET model for fully-depleted single drain and LDD devices," Solid-State Electronics*, Mar, 2000.
13.	Sheng-Lyang Jang, Chwan-Gwo Chyau, Chorng-Jye Sheu, "Complete Deep-Submicron Metal-Oxide-Semiconductor Field-Effect-Transistor Drain Current Model Including Quantum Mechanical Effects," Japanese Journal of Applied Physics*, Jan, 1999.
14.	Sheng-Lyang Jang, Shau-Shen Liu, and Chorng-Jye Sheu, "A Compact LDD MOSFET Model Based on Nonpinned Surface Potential," IEEE TRANSACTIONS ON ELECTRON DEVICES*, Dec, 1998.
15.	SHENG-LYANG JANG, TZ-HUA TANG, YOUNG-SHYING CHEN and CHORNG-JYE SHEU, "MODELING OF HOT-CARRIER STRESSED CHARACTERISTICS OF SUBMICROMETER pMOSFETs," Solid-State Elecrronics*, Jul, 1996.

國際性會議論文

1.	Chorng-Jye Sheu, "Modeling of Electron Substrate and Gate Current for Single-Drain Buried-Channel pMOSFETs," IEEE International Conference on Electron Devices and Solid-State Circuits, Dec, 2007.
2.	Chorng-Jye Sheu, "Modeling of Electron Gate Current and Post-Stress Drain Current for Buried-Channel pMOSFETs," International Electron Devices and Materials Symposium, Dec, 2007.

國內會議論文

1.	呂輝宗，李國全，許重傑, "摩擦模式對銅銲線製程第二銲點銲線接合的改善," ILT2014第九屆智慧生活科技研討會, Jun, 2014.
2.	呂輝宗，李國全，許重傑, "電漿清洗對銅銲線製程導線架導腳鍍銀面之改善," 2014 電子,信號,與通訊創新科技研討會, May, 2014.
3.	許郁昇，莊妙如，許重傑, "電化學法氧沈積化鋅薄膜：過氧化氫含量與沈積溫度的影響," 2012 台灣鍍膜科技協會年會(TACT 2012), Nov, 2012.
4.	呂輝宗，許健輝，許重傑, "顏色調控之有機發光二極體," 2012第六屆智慧型系統工程應用研討會, May, 2012.
5.	呂輝宗，李芳錡，許重傑, "電洞阻擋層在發光層不同位置之影響," 2011年奈米技術與材料研討會, Dec, 2011.
6.	呂輝宗，周冠呈，許重傑, "有機發光二極體電洞阻擋層與電洞注入層膜厚之改良," 2011年奈米技術與材料研討會, Dec, 2011.
7.	Chorng-Jye Sheu, "Measuring and Statistical Analysis of Chromaticity for Small-Size Dual-Display Backlight Modules," Proceeding of Optics and Photonics Taiwan, Dec, 2007.
8.	Chorng-Jye Sheu, "Measurement and Appraisal of Optical Characteristics for Small-Size Backlight Module," Proceeding of Optics and Photonics Taiwan, Dec, 2005.
9.	Chorng-Jye Sheu, "Measurement and Analysis of the Characteristics of Contrast Ratio and Response Time for Small Size Amorphous-Silicon Thin-Film-Transistors Liquid-Crystal Displays," Electron Devices and Materials Symposia, Nov, 2005.

計畫：

1. 小尺寸雙模顯示背光模組色座標量測與統計分析 (2008-01 ~ 2009-01)
2. 液晶顯示器產業的品質管理系統與工程技學素養課程之研究 (2006-08 ~ 2007-07)
3. 小尺寸非晶矽液晶平面顯示器光學特性量測系統之研究 (2005-05 ~ 2006-05)
4. 以自動化反射率光譜儀測量半導體材料薄膜之介電函數 (2002-08 ~ 2003-07)
5. 金氧半場效電晶體應力後具穿透機制之閘極電流模擬 (2001-08 ~ 2002-07)

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13. 建國科技大學104學年度日間部、進修學院(校)優良導師 (2015-09 ~ 2016-07)
14. ICT計算機綜合能力 - Essentials (CHT)國際證照 (2015-05)
15. 建國科技大學101學年度日間部優良導師 (2012-09 ~ 2013-07)
16. 991教學部落格競賽---佳作 (2010-09 ~ 2010-11)
17. International Biographical Centre Name Inclusions (2010-01 ~ 2010-12)
18. 建國科技大學98學年度優良導師 (2009-09 ~ 2010-06)
19. Marquis Who's Who Name Inclusions (2009-08)
20. 建國科技大學96學年度優良導師 (2007-09 ~ 2008-07)

帳號資訊

身份: 老師

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